\hypertarget{struct_i2_c___reg_def}{
\section{I2C\_\-RegDef Struct Reference}
\label{struct_i2_c___reg_def}\index{I2C\_\-RegDef@{I2C\_\-RegDef}}
}


structure of i2c parameters  




{\ttfamily \#include $<$i2c.h$>$}

\subsection*{Data Fields}
\begin{DoxyCompactItemize}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a78afe65cd40934d2825346694af63c48}{Ctrl}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a6ad4031fbefbcf4086428326d63b822c}{Scll}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a9161c30fd8310ab347a269b0cb319a3a}{Sclh}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_aedd8b811e35750fd90de77877c7c1275}{Stsu}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a3b0c458465954084ad1d2a4afe34ba94}{Sthd}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a4cc8fb9658b5b1326331be4aac1774ea}{Sosu}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_a0dc8ef7d87f586e50a77dfbd021cffb0}{Dtsu}
\item 
u8\_\-t \hyperlink{struct_i2_c___reg_def_aef69bf38065ba6bb06acd73b530c2bfe}{Dthd}
\end{DoxyCompactItemize}


\subsection{Detailed Description}
structure of i2c parameters 

\subsection{Field Documentation}
\hypertarget{struct_i2_c___reg_def_a78afe65cd40934d2825346694af63c48}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Ctrl@{Ctrl}}
\index{Ctrl@{Ctrl}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Ctrl}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Ctrl}}}
\label{struct_i2_c___reg_def_a78afe65cd40934d2825346694af63c48}
0:automatic dma address increment after each read/write 1: restart between write and read \hypertarget{struct_i2_c___reg_def_aef69bf38065ba6bb06acd73b530c2bfe}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Dthd@{Dthd}}
\index{Dthd@{Dthd}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Dthd}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Dthd}}}
\label{struct_i2_c___reg_def_aef69bf38065ba6bb06acd73b530c2bfe}
SDA hold clock count for data \hypertarget{struct_i2_c___reg_def_a0dc8ef7d87f586e50a77dfbd021cffb0}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Dtsu@{Dtsu}}
\index{Dtsu@{Dtsu}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Dtsu}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Dtsu}}}
\label{struct_i2_c___reg_def_a0dc8ef7d87f586e50a77dfbd021cffb0}
SDA setup clock count for data \hypertarget{struct_i2_c___reg_def_a9161c30fd8310ab347a269b0cb319a3a}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Sclh@{Sclh}}
\index{Sclh@{Sclh}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Sclh}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Sclh}}}
\label{struct_i2_c___reg_def_a9161c30fd8310ab347a269b0cb319a3a}
SCL high clock count \hypertarget{struct_i2_c___reg_def_a6ad4031fbefbcf4086428326d63b822c}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Scll@{Scll}}
\index{Scll@{Scll}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Scll}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Scll}}}
\label{struct_i2_c___reg_def_a6ad4031fbefbcf4086428326d63b822c}
SCL low clock count \hypertarget{struct_i2_c___reg_def_a4cc8fb9658b5b1326331be4aac1774ea}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Sosu@{Sosu}}
\index{Sosu@{Sosu}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Sosu}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Sosu}}}
\label{struct_i2_c___reg_def_a4cc8fb9658b5b1326331be4aac1774ea}
SDA setup clock count at stop \hypertarget{struct_i2_c___reg_def_a3b0c458465954084ad1d2a4afe34ba94}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Sthd@{Sthd}}
\index{Sthd@{Sthd}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Sthd}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Sthd}}}
\label{struct_i2_c___reg_def_a3b0c458465954084ad1d2a4afe34ba94}
SDA hold clock count at start \hypertarget{struct_i2_c___reg_def_aedd8b811e35750fd90de77877c7c1275}{
\index{I2C\_\-RegDef@{I2C\_\-RegDef}!Stsu@{Stsu}}
\index{Stsu@{Stsu}!I2C_RegDef@{I2C\_\-RegDef}}
\subsubsection[{Stsu}]{\setlength{\rightskip}{0pt plus 5cm}u8\_\-t {\bf Stsu}}}
\label{struct_i2_c___reg_def_aedd8b811e35750fd90de77877c7c1275}
SDA setup clock count at start 

The documentation for this struct was generated from the following file:\begin{DoxyCompactItemize}
\item 
i2c.h\end{DoxyCompactItemize}
